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ac101l-ds06-405-r 16215 alton parkway ? p.o. box 57013 irvine, california 92619-7013 phone: 949-450-8700 fax: 949-450-8710 8/9/04 preliminary data sheet ac101l ultra low-power 10/100 ethernet transceiver with auto-mdix figure 1: functional block diagram g eneral description f eatures the ac101l is a single-channel, low-power, 10/100base-tx/fx transceiver. the ac101l transceiver has an integrated voltage regulator to allow operation from a single 3.3v or 2.5v supply source. the device contains a full-duplex 10base-t/100base-tx/ 100base-fx fast ethernet transceiver, which performs all of the physical layer interface functions. the ac101l is a highly integrated solution combining an encoder/decoder, link monitor, auto-negotiation selection, parallel detection, adaptive equalization, clock/ data recovery, baseline wander correction, multimode transmitter, scrambler/descr ambler, far-end fault (fef), and auto-mdi/mdix circuitry. ? 3.3v tolerant and 2.5v capable integrated voltage regulator to allow operation from a single 3.3v or 2.5v supply source 10/100 tx/fx full-duplex or half-duplex fefi on 100fx 48-pin tqfp industrial temperature (?40 c to +85 c) 0.25 m cmos fully compliant with ieee 802.3/802.3u mii interface baseline wander correction multifunction led outputs cable length indicator hp auto-mdi/mdix eight programmable interrupts diagnostic registers phyad[4:0] rxn/rx p txn/txp 100rx mii data interface 25 mhz 100tx 10tx 10rx mii serial interface flp rx control status pcs framer carrier 4b/5b pma clock recov. link monitor signal detect tp_pmd mlt3 blw stream cipher mux auto-negotiation pll clk gen. test/led control mii serial management interface and register interface mac 10base-t xtli/clkin led drivers 25 mhz
ac101l preliminary data sheet 8/9/04 broadcom corporation page ii document ac101l-ds06-405-r r evision h istory revision date change description ac101l-ds06-r 8/9/04 edits for consistency, minor error corrections ac101l-ds05-r 3/10/03 replaced the # sign with an overline to indicate active low pins. in table 1, changed description of pin 24 (pdown ) from being pulled low externally to being pulled high externally for normal operation. ac101l-ds04-r 1/29/03 updated table 1, ?pinout and signal definitions,? on page 7. updated figure 2, ?ac101l pinout diagram,? on page 11. updated table 19, ?register 23: operation mode register,? on page 25. updated table 22, ?common register 1: (map to reg. 29, page 0 a28.[15:12]=0000) test mode register,? on page 26. updated table 23, ?common register 4: (map to reg. 29, page 1 a28.[15:12]=0001) led blink rate,? on page 27. updated table 44, ?recommended operating conditions,? on page 46. ac101l-ds03-r 9/18/02 updated signal types designations in section 2 ?pin descriptions? on page 7. updated table 35, ?reset timing,? on page 35. updated table 37, ?100base-x mii transmit system timing,? on page 37. updated table 38, ?100base-tx/fx mii receive system timing,? on page 38 and figure 6, ?100base-t mii receive timing,? on page 39. updated table 39, ?10base-t mii transmit system timing,? on page 40 and figure 7, ?10base-t transmit timing,? on page 40. updated table 40, ?10base-t mii receive system timing,? on page 41 and figure 8, ?10base-t receive timing,? on page 42. removed table 42,?rmii receive timing,? on page 39 and figure 9,?rmii receive timing,? on page 39 as well as all references to rmii in the document. updated table 44, ?recommended operating conditions,? on page 46. ac101l-ds02-r 6/6/02 added table showing current requirements at 2.5 v operation with led disabled. added table showing current requirements at 3.3 v operation with led disabled. added output voltage high values and output voltage low values (all digital pins). added input voltage high and low values (all digital input pins). ac101l-ds01-r 02/20/02 updated fx application figure and power and ground filtering figure. AC101L-DS00-R 01/02/02 initial release.
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-405-r page iii
altima communications, inc. a wholly-owned subsidiary of broadcom corporation p.o. box 57013 16215 alton parkway irvine, california 92619-7013 ? 2004 by altima communications, inc. all rights reserved altima communications, broadcom, and the pulse logo are registered trademarks of broadcom corporation and/or its subsidiaries in the united states and certain other countries. any other trademarks are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as- is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the im plied warranties of merchantability, fitness for a particular purpose, and non-infringement.
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r page v table of contents section 1: functional description ...................................................................................... 1 encoder/decoder ............................................................................................................................... .......... 1 link monitor ............................................................................................................................... ................... 1 carrier sense (crs)/rxdv .......................................................................................................................... 2 collision detection ............................................................................................................................... ........ 2 auto-negotiation ............................................................................................................................... ........... 2 parallel detection ............................................................................................................................... .......... 3 analog adaptive equalizer .......................................................................................................................... 3 clock recovery ............................................................................................................................... ............. 3 baseline wander correction ....................................................................................................................... 4 multimode transmitter ............................................................................................................................... .4 stream cipher scrambler/descrambler ..................................................................................................... 4 fef (far-end fault) ............................................................................................................................... ....... 5 transmit driver ............................................................................................................................... .............. 5 hp auto-mdi/mdix ............................................................................................................................... ........ 5 mac interface ............................................................................................................................... ................ 6 mii ............................................................................................................................ ............................... 6 smi............................................................................................................................ .............................. 6 physical layer interfaces ............................................................................................................................ 6 section 2: pin descriptions ................................................................................................ 7 section 3: pinout diagram ..................................................................................................9 section 4: operational description ..................................................................................10 reset ............................................................................................................................... ............................ 10 power source ............................................................................................................................... .............. 10 power saving mode ............................................................................................................................... .... 10 clock source ............................................................................................................................... ............... 11 isolate mode ............................................................................................................................... ................ 11 loopback mode ............................................................................................................................... ........... 11 interrupt mode ............................................................................................................................... ............. 11 led operation ............................................................................................................................... ............. 11 led interface .................................................................................................................. ...................... 11
ac101l preliminary data sheet 8/9/04 broadcom corporation page vi document ac101l-ds06-r led configuration .............................................................................................................. ...................12 led [3:0] event table .......................................................................................................... .................12 section 5: register description ....................................................................................... 13 tp phy register summary ........................................................................................................................13 register 0: control register .................................................................................................. ...............14 register 1: status register ................................................................................................... ................14 register 2: phy identifier 1 register ......................................................................................... ...........16 register 3: phy identifier 2 register ......................................................................................... ...........16 register 4: auto-negotiation advertisement register ..........................................................................1 6 register 5: auto-negotiation link partner ability register/link partner next page message ..............17 register 6: auto-negotiation expansion register ................................................................................ .17 register 7: auto-negotiation next page transmit register ..................................................................18 register 16: bt and interrupt level control register........................................................................... .18 register 17: interrupt control/status register................................................................................. ......19 register 18: diagnostic register ............................................................................................... ............19 register 19: power/loopback register ........................................................................................... ......20 register 20: cable measurement capability register...........................................................................20 register 21: receive error counter ............................................................................................. .........21 register 22: power management register......................................................................................... ...21 register 23: operation mode register ........................................................................................... .......21 register 24: crc for recent received packet.................................................................................... .22 common registers ............................................................................................................................... ......22 common register 0 (map to reg28) mode control register................................................................22 common register 1: (map to reg. 29, page 0 a28.[15:12]=0000) test mode register ......................23 common register 4: (map to reg. 29, page 1 a28.[15:12]=0001) led blink rate .............................23 common register 5: (map to reg. 30, page 1 a.28.[15:12]=0001) led0 setting1 register ...............23 common register 6: (map to reg. 31, page 1 a.28.[15:12]=0001) led0 setting2 register ...............24 common register 7: (map to reg. 29, page 2 a.28.[15:12]=0010) led1 setting1 register ...............24 common register 8: (map to reg. 30, page 2 a.28.[15:12]=0010) led1 setting2 register ...............24 common register 9: (map to reg. 31, page 2 a.28.[15:12]=0010) led2 setting1 register ...............24 common register 10: (map to reg. 29, page 3 a.28.[15:12]=0011) led2 setting2 register .............25 common register 11: (map to reg. 30, page 3 a.28[.15:12]=0011) led3 setting1 register .............25 common register 12: (map to reg. 31, page 3 a.28.[15:12]=0011) led3 setting2 register .............25
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r page vii section 6: 4b/5b code group ........................................................................................... 26 section 7: smi read/write sequence ............................................................................... 27 section 8: timing and ac characteristics ...................................................................... 28 clock timing ............................................................................................................................... ................ 28 reset timing ............................................................................................................................... ................ 28 management data interface timing ........................................................................................................... 29 100base-tx/fx mii transmit system timing ......................................................................................... 29 100base-tx/fx mii receive system timing ........................................................................................... 31 10base-t mii transmit system timing ................................................................................................... 33 10base-t mii receive system timing ..................................................................................................... 34 copper application termination ............................................................................................................... 36 section 9: electrical characteristics ................................................................................ 37 absolute maximum ratings ...................................................................................................................... 37 recommended operating conditions ...................................................................................................... 38 section 10: fiber app lication termination ...................................................................... 39 section 11: power and ground filtering .........................................................................40 section 12: mechanical information ................................................................................. 41 section 13: thermal parameters ...................................................................................... 42 section 14: ordering information ..................................................................................... 43
ac101l preliminary data sheet 8/9/04 broadcom corporation page viii document ac101l-ds06-r l ist of f igures figure 1: functional block diagram ............................................................................................. ........................ i figure 2: ac101l pinout diagram ................................................................................................ ...................... 9 figure 3: reset timing......................................................................................................... .............................28 figure 4: management interface timing .......................................................................................... .................29 figure 5: 100base-tx/fx mii transmit timing .................................................................................... ...........30 figure 6: 100base-t mii receive timing ......................................................................................... ...............32 figure 7: 10base-t transmit timing ............................................................................................. ..................33 figure 8: 10base-t receive timing .............................................................................................. ..................35 figure 9: tx application....................................................................................................... .............................36 figure 10: fx application...................................................................................................... ............................39 figure 11: power and ground filtering .......................................................................................... ...................40 figure 12: quad flat pack outline (77 mm) ..................................................................................... ...............41
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r page ix l ist of t ables table 1: auto-negotiation mode................................................................................................. ........................ 2 table 2: pinout and signal definitions......................................................................................... ....................... 7 table 3: led [3:0] event table ................................................................................................. ....................... 12 table 4: tp phy register summary............................................................................................... ................. 13 table 5: register 0: control register .......................................................................................... ..................... 14 table 6: register 1: status register........................................................................................... ...................... 14 table 7: register 2: phy identifier 1 register................................................................................. ................. 16 table 8: register 3: phy identifier 2 register................................................................................. ................. 16 table 9: register 4: auto-negotiation advertisement register ................................................................... ..... 16 table 10: register 5: auto-negotiation link partner ability register/link partner next page message ......... 17 table 11: register 6: auto-negotiation expansion register ...................................................................... ...... 17 table 12: register 7: auto-negotiation next page transmit register ............................................................. 18 table 13: register 16: bt and interrupt level control register................................................................. ...... 18 table 14: register 17: interrupt control/status register....................................................................... ........... 19 table 15: register 18: diagnostic register ..................................................................................... ................. 19 table 16: register 19: power/loopback register ................................................................................. ........... 20 table 17: register 20: cable measurement capability register................................................................... ... 20 table 18: register 21: receive error counter ................................................................................... .............. 21 table 19: register 22: power management register............................................................................... ........ 21 table 20: register 23: operation mode register ................................................................................. ............ 21 table 21: register 24: crc for recent received packet.......................................................................... ...... 22 table 22: common register 0 (map to reg. 28) mode control register......................................................... 22 table 23: common register 1: (map to reg. 29, page 0 a28.[15:12]=0000) test mode register ................. 23 table 24: common register 4: (map to reg. 29, page 1 a28.[15:12]=0001) led blink rate ........................ 23 table 25: common register 5: (map to reg. 30, page 1 a.28.[15:12]=0001) led0 setting1 register .......... 23 table 26: common register 6: (map to reg. 31, page 1 a.28.[15:12]=0001) led0 setting2 register .......... 24 table 27: common register 7: (map to reg. 29, page 2 a.28.[15:12]=0010) led1 setting1 register .......... 24 table 28: common register 8: (map to reg. 30, page 2 a.28.[15:12]=0010) led1 setting2 register .......... 24 table 29: common register 9: (map to reg. 31, page 2 a.28.[15:12]=0010) led2 setting1 register .......... 24 table 30: common register 10: (map to reg. 29, page 3 a.28.[15:12]=0011) led2 setting2 register ........ 25 table 31: common register 11: (map to reg. 30, page 3 a.28[.15:12]=0011) led3 setting1 register ........ 25 table 32: common register 12: (map to reg. 31, page 3 a.28.[15:12]=0011) led3 setting2 register ........ 25 table 33: 4b/5b code group ..................................................................................................... ...................... 26
ac101l preliminary data sheet 8/9/04 broadcom corporation page x document ac101l-ds06-r table 34: smi read/write sequence .............................................................................................. .................27 table 35: clock timing ......................................................................................................... ............................28 table 36: reset timing ......................................................................................................... ............................28 table 37: management interface timing .......................................................................................... ................29 table 38: 100base-x mii transmit system timing ................................................................................. ........29 table 39: 100base-tx/fx mii receive system timing .............................................................................. ....31 table 40: 10base-t mii transmit system timing .................................................................................. .........33 table 41: 10base-t mii receive system timing ................................................................................... .........34 table 42: absolute maximum ratings ............................................................................................. .................37 table 43: current requirement at 2.5v operation with led disabled .............................................................3 7 table 44: current requirement at 3.3v operation with led disabled .............................................................3 7 table 45: recommended operating conditions ..................................................................................... ..........38 table 46: thermal parameters ................................................................................................... ......................42 table 47: ordering information ................................................................................................. ........................43
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r functional description page 1 section 1: functional description the ac101l is a single-chip, fast ethernet transceiver. it performs all of the physical layer interface functions for 100base-tx full-duplex or half-duplex on category 5 twist ed-pair cable, and 10base-t full-duplex or half-duplex on category 3 cable. it can be configured for 100base-fx full- or half-duplex transmission over fiber-optic cable when paired with an external fiber-optic line driver and receiver. the chip performs 4b5b, mlt3, nrzi, encoder/decoder, link monitor, auto-negotiation selection, adaptive equalization, clock/data recovery, baseline wander correction, multimode tr ansmitter, scrambler/descrambl er, far-end fault (fef), and auto-mdi/mdix. it can be connected to a mac switch controller through the mii on one side and directly to the media on the other side through a transformer for twisted-pair (tp) mode, or fiber-optic module for fx mode. it is fully compliant with the ieee 802.3 and 803.3u standards. e ncoder /d ecoder in 100base-tx and 100base-fx modes, the ac101l transmits and receives data stream on tw isted-pair or fiber-optic cable. when the mii transmit enable is asserted, nibble wide (4-bit) data from transmit data pins is encoded into 5-bit code groups and inserted into transmit data stream. the 4b/5b encoding is shown in section 6: ?4b/5b code group? on page 26. the transmit packet is encapsulated by replacing the first 2 nibbles of preamble with a start of stream delimiter (j/k codes) and appending an end of stream delimiter (t/r codes) to the end of packet. when the mii transmit error input is asserted during a packet, the error code group (h) is sent in pl ace of the corresponding data code group. the transmitter sends repeatedly the idle code group between packets. in 100base-tx mode, the encode data stream is first scrambled by a stream cipher block and then serialized and encoded into an mlt3 signal level. second, a multimode transmit dac (digital to analog converter) is used to drive the mlt3 data onto twisted-pair cable. following baseline wander correc tion, adaptive equalization and clock/data recovery in 100base- tx mode, the receive data stream is converted from mlt3 to serial nrz data. the nrz data are descrambled by the stream cipher block and then deserialized and aligned into 5-bit code groups. in 100base-fx mode, the scrambling function is bypassed and the data are nrzii-encoded. the multi mode transmit dac drives differential positive ecl (pecl) levels to an exter nal fiber-optic transmitter. baseline wander correction, adaptive equalization, stream cipher descrambling functions are bypassed and nrzi decoding is used instead of mlt3. the 5-bit code groups are decoded into 4-bit data nibbles. the start of stream delimiter is replaced with preamble nibbles and the end of stream delimiter and idle codes are replaced with all zeros. the decoded data are driven onto the mii receive data pins. when an invalid code group or bad ssd is detected in the data stream, the ac101l asserts the mii rxer signal. in 10base-t mode, manchester encoding and decoding is performed on the data stream. the multi mode transmit dac performs pre-equalization for 100 meters of category 3 cable. l ink m onitor in 100base-tx mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. the signal levels are qualified using squelch detect circuits. when no signal or certain valid signal is detected on the receive pa ir for a minimum period of time, the link monitor enters the link pass state, and the transmit and receive functions are enabled.
ac101l preliminary data sheet 8/9/04 broadcom corporation page 2 carrier sense (crs )/rxdv document ac101l-ds06-r in 100base-fx mode, the external fiber-optic receiver performs the signal energy detection function and communicates this information directly to the sd signal (pin 28). in 10base-t mode, a link pulse detection circuit constantly monitors the rxp/rxn pins for the presence of valid link pulses. c arrier s ense (crs)/rxdv carrier sense is asserted asynchronously on the crs pins as soon as activity is detected on the receive data stream. rxdv is asserted as soon as a valid ssd (start-of-stream delimiter) is detected. carrier sense and rxdv are de-asserted synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data stream. however, if the carrier sense is asserted and a valid ssd is not detected immediately, rxer is asserted instead of rxdv. in 10base-t mode, crs is asserted asynchronously when the valid preamble and data activity is detected on the rxip and rxin pins. in the half-duplex mode, the crs is activated during data transmit. in the full-duplex mode, the crs is activated during data receiving only. c ollision d etection in half-duplex mode, collision detect is asserted on the col pin whenever carrier sense is asserted and transmission is in progress. a uto -n egotiation auto-negotiation selection is on 100base twisted-pair phy only; it is not operating in 100base fiber phy. in 100base-tx mode, auto-negotiation can be enabled or disabled by hardware or software control. when the auto- negotiation function is enabled, the 100base-tx phy automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its link partner. 100base-tx phy can be configured to advertise 100base- tx full-duplex or 100base-tx half-duplex. the default auto-negotiation mode is configured via reset read value of anen/led3 signal (pin 23) and spd100/led1. table 1: auto-negotiation mode mode mode name link settings 0.13 speed select the default value is spd100. 0.12 anen enable 1 = enable auto-negotiation. 0 = disable auto-negotiation. 0.8 duplex the default value is !anen && duplex. 4.8/1.14 100base-tx full-duplex the default value of this bit is spd100 && duplex.
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r parallel detection page 3 p arallel d etection because there are many devices in the field that do not support the anen process, but must still be communicated with, it is necessary to detect and link through the parallel detection process. the parallel detection circuit is enabled in the absenc e of flps. the circuit is able to detect the following: normal link pulse (nlp) 10base-t receive data 100base-tx idle the mode of operation gets configured based on the technology of the incoming signal. if any of the above is detected, the device automatically configures to match the detected operating speed in the half-duplex mode. this ability allows the device to communicate with the legacy 10base-t and 100base-tx systems, while maintaining the flexibility of auto-negotiation. a nalog a daptive e qualizer the analog adaptive equalizer removes intersymbol interference (isi) created by the transmission channel media. the phy is designed to accommodate a maximum of 140 meters of utp category 5 cable. an at&t 1061 category 5 cable of this length typically has an attenuation of 31 db at 100 mhz. a typical attenuation of 100-meter cable is 21 db. the worst case cable attenuation is around 24?26 db as defined by tp-pmd specification. the amplitude and phase distortion from the cable causes isi which makes clock and data recovery difficult. the adaptive equalizer is designed to closely match the inverse transfer function of the twisted-pair cable. the equaliz er has the ability to changes its equalizer frequency response according to the cable length. the equalizer will tune itself automatically for any cable, compensating for the amplitude and phase distortion introduced by the cable. c lock r ecovery the equalized mlt3 signal passes through the slicer circuit and is converted to nrzi format. the phy uses a proprietary mixed-signal phase locked loop (pll) to extract clock information from the incoming nrzi data. the extracted clock is used to retime the data stream and set the data boundaries. the transmit clock is locked to the 25-mhz clock input while the receive clock is locked to the incoming data streams. when initial lock is achieved, the pll switches to the data stream, extracts the 125-mhz clock, and uses it for the bit framing fo r the recovered data. the recovered 125-mhz clock is also used to generate the 25-mhz rx_clk signal. the pll requires no external components for its operation and has high noise immunity and low jitter. it provides fast phase alignment and locks to data in one transition. its data/clock acquisition time, after power-on, is less than 60 transitions. the pll can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. when no valid data are present (that is, when the sd is deasserted), the pll switches and locks on to 4.7/1.13 100base-tx the default value is spd100 && (anen || !duplex). 4.6/1.12 10base-t full-duplex the default value of this bit is duplex && (anen || !spd100). 4.5/1.11 10base-t the default value is anen || (!spd100 && !duplex). table 1: auto-negotiation mode (cont.) mode mode name link settings
ac101l preliminary data sheet 8/9/04 broadcom corporation page 4 baseline wander correction document ac101l-ds06-r tx_clk. this provides a continuously running rx_clk. at the pcs interface, the 5-bit data rxd[4:0] is synchronized to the 25-mhz rx_clk. b aseline w ander c orrection a 100base-tx data stream is not always dc-balanced. because the receive signal must pass through a transformer, the dc offset of the differential receive input can wander. this effect, known as baseline wander, can greatly reduce the noise immunity of the receiver. the 100base-tx phy automatically compensates for baseline wander by removing the dc offset from the input signal, thereby significantly reducing the chance of a receive symbol error. the baseline wander circuit is not required in 100base-fx phy operation. m ultimode t ransmitter the multimode transmitter transmits mlt3 coded symbols in 100base-tx mode, and nrzi coded symbols in 100base-fx mode. it utilizes a current drive output, which is well balanced and produces very low noise transmit signals. pecl voltage levels are produced with resistive terminations in 100base-fx mode. the serialized data bypasses the scrambler and 4b/5b encoder in fx mode. the output data are nrzi pecl signals. the pecl level signals are used to drive the fiber-optic transmitter. s tream c ipher s crambler /d escrambler in 100base-tx mode, the transmit data stream is scrambled to reduce radiated emissions on the twisted-pair cable. the data are scrambled by exclusive oring the nrz signal with the output of an 11-bit wide linear feedback shift register (lfsr), which produces a 2047-bit nonrepeating sequence. the scrambler reduces peak emission by randomly spreading the signal energy over the transmit frequency range and eliminating peaks at certain frequencies. the receiver descrambles the incoming data stream by ex clusive oring it with the same sequence generated at the transmitter. the descrambler detects the state of the transmit lfsr by looking for a sequence representing consecutive idle codes. the descrambler locks to the scrambler state after detecting a sufficient number of consecutive idle code group. the receiver does not attempt to decode the data stream unless the descrambler is locked. when locked, the descrambler continuously monitors the data stream to make sure that it has not lost synchronization. the receive data stream is expected to contain inter-packet idle periods. if the descrambler does not detect enough idle code within 724 s, it becomes unlocked and the receive decoder is disabled. the descrambler is always forced into the unlock state when a link failure condition is detected. stream cipher descrambler is not used in the 100base-fx mode.
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r fef (far-end fault) page 5 fef (f ar -e nd f ault ) auto-negotiation provides the mechanism to inform the link pa rtner that a remote fault has occurred. auto-negotiation is disabled, however, in the 100base-fx applications. an alte rnative in-band signaling function (fefi) is used to signal a remote fault condition. fefi is a stream of 84 consecutive ones followed by one logic zero. this pattern is repeated three times. an fefi signal is given under three conditions: when no activity is received from the link partner. when the clock recovery circuit detects a signal error or pll lock error. when a management entity sets the transmit far-end fault bit. the fefi mechanism is enabled by default in the 100base-fx mode and disabled in 100base-tx or 10base-t modes. the register setting can be changed by software after reset. t ransmit d river in 100base-tx mode, the phy transmit function converts synchr onous 4-bit data nibbles from the mii to a pair of 125-mbps differential serial data streams. the serial data are transmitte d over network twisted-pair cabl es via an isolation transformer . data conversion includes 4b/5b encoding, scrambling, para llel-to-serial, nrz to nrzi, and mlt3 encoding. the entire operation is synchronous to the 25-mhz and 125-mhz clocks. both clocks are generated by an on-chip pll clock synthesizer that is locked on to an external 25-mhz clock source. in 100base-fx, the transmit driver does not perform filtering; it utilizes a curr ent drive output that is well balanced and produces a low noise pecl signal. pecl voltage levels are produced with resistive terminations. in 10base-t mode, if the mii interface is used, parallel-to-serial logic is used to convert the 4-bit data into the serial stre am through the output wave shaping driver. the wave shaper reduces any emi emission by filtering out the harmonics, therefore eliminating the need for an external filter. hp a uto -mdi/mdix this feature is able to detect the required cable connecti on type (straight-through or crossed-over) and make correction automatically.
ac101l preliminary data sheet 8/9/04 broadcom corporation page 6 mac interface document ac101l-ds06-r mac i nterface mii the media independent interface (mii) is an 18-wire mac/ph y interface described in ieee 802.3u. the purpose of the interface is to allow mac layer devices to attach to a va riety of physical layer devices through a common interface. mii operates at either 100 mbps or 10 mbps, depending on the speed of the physical layer. with clocks running at either 25 mhz or 2.5 mhz, 4-bit data are clocked between the mac and phy, synchronously with enable and error signals. at the time of pll lock on an incoming signal from the wire interface, the phy generates rx_clk at either 2.5 mhz for 10 mbps or 25 mhz for 100 mbps. on receipt of valid data from the wire interface, rxdv goes active signaling the mac that valid data will be presented on the rxd[3:0] pins at the speed of the rx_clk. on transmission of data from the mac, txen is presented to the phy, indicating the presence of valid data on txd[3:0]. txd[3:0] are sampled by the phy( synchronous to tx_clk) during the time that txen is valid. smi the phys internal registers are accessible only through the mii 2-wire serial management interface (smi). mdc is a clock input to the phy, which is used to latch in or out data and instructions for the phy. the clock can run at any speed from dc to 25 mhz. mdio is a bidirectional connection used to write instructions to, write data to, or read data from the phy. each data bit is latched either in or out on the rising edge of the mdc. the mdc is not required to maintain any speed or duty cycle, provided no half cycle is less than 20 ns, and that data are presented synchronous to the mdc. mdc/mdio are a common signal pair to all phys on a design. therefore, each phy needs to have its own unique physical address. the physical address of the phy is set using the pins defined as phyad[4:0]. these input signals are strapped externally, and are sampled as reset is negated. at idle, the phy is responsible to pull the mdio line to a high state. therefore, a 1 k ? resistor is required to connect the mdio line to vcc. p hysical l ayer i nterfaces the two supported interfaces are the twisted-pair (tp) interface with auto-mdi/mdix selection, and the fiber-optic interface with pecl signaling. the selection of these two interfaces is performed at reset time by the sd/fxen signal (pin 28). pull pin 28 low to enable the tp interface, or connect pin 28 to the fiber module to enable fx interface.
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r pin descriptions page 7 section 2: pin descriptions many pins perform multiple functions. these pins are designated by a bold pin number, and their descriptions are listed in the proper sections. designers must verify that they have taken into account all modes of operation prior to final design. signal types: b = bidirection pin p= power pin g = ground pin ai = analog input pin ao = analog output pin d = internal pull-down pin u = internal pull-up pin overline = active low all digital pins are bidirectional pins. table 2: pinout and signal definitions pin number pin name type description 1 vcc p +2.5v power supply. 2 gnd g ground. 2 gnd g ground. 3rxdv b d rxdv (active high output): receive data valid is the output signal in the mii mode. rxdv is active high to indicate that the receive frame is in progress, and that the data stream present on the rxd output pins is valid. 4rx_clk b d input function is reserved. this pin must be pulled low externally. rx_clk (output): receive clock in mii mode. rx_clk is 25-mhz output in 100base and 2.5 mhz output in 10base. this clock is recovered from the incoming data on the cable inputs. 5rxer b d input function is reserved. this pin must be pulled low externally. rxer (active high output): asserted to indicate that an invalid symbol or bad ssd is detected in mii modes. 6 gnd g ground. 7 vcc p +2.5v power supply. 8 txer b d txer (active high input): transmits an error in the mii interface. when txer is asserted for one or more tx_clk periods while txen is also asserted, the phy emits one or more symbols that are not part of the valid data or delimiter set somewhere in the frame being transmitted. the relative position of the error within the frame need not be preserved. 9tx_clk b d tx_clk (output): transmits the clock signal of the mii mode. tx_clk is 25-mhz output in 100base operation and 2.5-mhz in 10base operation. this clock is a continuously-driven output, generated from the xi (crystal input) pin. 10 txen b d txen (active high input): transmits the enable signal in the mi i interfaces. txen is asserted by the mac to indicate that valid data are present on txd[3:0]. 11 txd0 b d txd0: transmits data input for the mii interface. 12 txd1 b d txd1: transmits data input for the mii interface. 13 txd2 b d txd2: transmits data input for the mii interface. 14 txd3 b d txd3: transmits data input for mii interface. 15 col b d col (active high output): this pin must be pulled low externally. it is the collision detect signal in the mii interface. in ha lf- duplex mode, col active high output indicates that a collision has occurred. in full-duplex mode, col remains low. 16 repeater/ crs b d repeater: resets read input. active high puts the chip in repeater mode. crs (active high output): carrier sense signal in the mii interface. crs is asserted when the twisted-pair media is non- idle and is deasserted when idle, or when a valid end-of-stream delimiter is detected. 17 gnd g ground. 18 vcc p +2.5v power supply. 19 phyad0/ intr b u phyad0: resets read input. pull high or low to set the phy address bit 0 for the mii management function. intr (output): active low interrupt output. cleared by reading register 17.
ac101l preliminary data sheet 8/9/04 broadcom corporation page 8 pin descriptions document ac101l-ds06-r 20 burnin / led0 b u burnin : resets read input. set active low to put the chip in burn-in test mode. led0 (output): active low, the default behavior is on when the chip is in link-up condition, and is blink when the chip detects transmit or receive activity. 21 spd100/ led1 b u spd100: resets read input. if anen is low, spd100 sets the tp port speed in register 0. if anen is high, spd100 is used to set 100 mbps half-duplex and 100 mbps full-duplex bits in register 4. led1 (output): active low. the default behavior is on when the chip is operating at 100 mbps and is off when the chip is operating at 10 mbps. 22 duplex/ led2 b u duplex: resets read input. if anen is low, duplex sets the tp port in full-duplex mode in register 0. if anen is high, duplex is used to set 10 mbps fdx and 100 mbps fdx bits in register 4. led2 (output): active low. the default behavior is on when the chip is operating in full-duplex mode and is off when the chip is operating in half-duplex mode. 23 anen/led3 b u anen (resets read input): auto-negotiation enable for the twisted-pair port. pull high to enable auto-negotiation. pull low to disable auto-negotiation. led3 (output): active low. the default behavior is blink when the chip detect collision is in half-duplex mode. 24 pdown b u pdown (input): power-down input. this pin must be pulled high externally for normal operation. pulling this pin low puts both the tp and fiber port into power-down mode. this is a regular input, not a reset read signal. 25 vcc p +2.5v power supply. 26 rxn a receive. for tp port in mdi mode. transmit. for tp port in mdix mode. 27 rxp a receive +. for tp port in mdi mode. transmit +. for tp port in mdix mode. 28 sd/fxen ai sd/fxen (analog input): this pin must be pulled low externally for normal tp mode. connect to fiber module to enable fx mode; also serves as signal detect input. 29 gnd g ground. 30 gnd g ground. 31 rbiad a bias resistor connection. connect to a 10k 1% resistor to gnd. 32 vccpll p +2.5v supply for analog bias, pll modules. 33 gnd g ground. 34 txn a transmit. in mdi mode. receive. in mdix mode. 35 txp a transmit +. in mdi mode. receive +. in mdix mode. 36 vcc25out p +2.5vcc out from the on-chip regulator. 37 gnd g ground. 38 gnd g ground. 39 xo a xtal output. 40 xi a xtal input. in mii mode: xi and xo is designed to connect to a 25 mhz., 50 ppm xtal or 25 mhz osc. 41 vcc33in p 3.3v power supply input. 42 rst i u reset input. active low. 43 mdio b u mdio (input/ output): management data i/o. this serial input/output pin is used to read from and write to the mii register. the data value on the mdio pin is valid and latched on the rising edge of the mdc. this pin requires a 1 k ? resistor pull-up. 44 mdc i d mdc (input): management data clock. this pin must be pulled low externally for normal operation. the mdc clock input must be provided to allow mii management function. this pin has a schmitt trigger input. 45 phyad1/ rxd3 b d phyad1: resets read input. pull high or low to set the phy address bit 1 for mii management function. rxd3: receives the data output signal in the mii interface. 46 phyad2/ rxd2 b d phyad2: resets read input. pull high or low to set the phy address bit 2 for mii management function. rxd2: receives the data output signal in the mii interface. 47 phyad3/ rxd1 b d phyad3 (reset read input): pull high or low to set the phy address bit 3 for mii management function. rxd1: receive data output signal in mii interface. 48 phyad4/ rxd0 b d phyad4: resets read input. pull high or low to set the phy address bit 4 for mii management function. rxd0: receives the data output signal in the mii interface. table 2: pinout and signal definitions (cont.) pin number pin name type description
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r pinout diagram page 9 section 3: pinout diagram figure 2: ac101l pinout diagram rx_clk txer gnd txen txd1 ac101l txd3 repeater/crs vcc vcc pdown# rxn burnin#_l/led0 duplex/led2 sd/fxen gnd vccpll txn vcc25ou t rxdv rxer txc vcc txd0 txd2 col gnd vcc spd100/led1 anen/led3 phyad0/intr rxp gnd 48tqfp_7x7mm rbiad gnd txp gnd gnd mdio phyad1/rxd 3 phyad3/rxd 1 gnd xi rst# mdc phyad2/rxd 2 phyad4/rxd 0 xo vcc33in 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37
ac101l preliminary data sheet 8/9/04 broadcom corporation page 10 operational description document ac101l-ds06-r section 4: operational description r eset the phy can be reset in two ways: hardware reset: (see ?pin descriptions? on page 7). software reset: (see ?register description? on page 13). p ower s ource the ac101l chip provides an onboard 3.3v 5% input to 2.5v 5% output regulator with the capability to drive 150 ma of current. the 2.5v output supplies the phy operation, including the leds. it is recommended to limit the led current below 10 ma per led. the 2.5v power should be decoupled to provide the digital and analog pins on the chip. p ower s aving m ode the power consumption of the ac101l device is significantly reduced due to its built-in power management features. separate power supply lines are used to power the 10base-t ci rcuitry and the 100base-tx circuitry. therefore, the two circuits can be turned on and turned off independently. when the phy is set to operate in 100base-tx mode, 10base-t circuitry is powered down. the following power management features are supported: power-down mode : (see pin and register descriptions). during power down mode, the device is still able to interface through the management interface. energy detect/power saving mode : energy detect mode turns off the power to select internal circuitry when there is no live network connected. the energy detect (ed) circuit is always turned on to monitor if there is signal energy present on the media. the management circuitry is also powered on and ready to respond to any management transaction. the transmit circuit still sends out link pulses with minimum power consumption. if a valid signal is received from the media, the device powers up and resumes normal transmit/receive operations. valid data detection mode : this can be achieved by writing to the receive clock register control bit. during this mode, if there is no data other than incoming idles, the receive clock (rx_clk) turns itself off. this could save the power of the attached media access controller. rx_clk re sumes operation one clock period prior to the assertion of rxdv. the receive clock again shuts off 64 clock cycles after rxdv is deasserted.
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r clock source page 11 c lock s ource the clock source for this chip is from the xi pin. in mii mode, it can connect to a 25 mhz 50 ppm (parts per million) osc or a 25 mhz 50 ppm xtal (crystal). i solate m ode when the ac101l device is put into isolate mode, all mii inputs (txd[3:0}, txen, txer) are ignored, and all mii outputs (tx_clk, col, crs, rx_clk, rxdv, rxer, rxd[3:0] are set to high impedance. only the mii management pins (mdc, mdio) operate normally. pull high pin 4 at reset or write 1 to bit 10 register 0 to put the chip into isolate mode. l oopback m ode local loopback is provided for testing purpose. it can be enabled by writing a one to register 0 bit 14. the local loopback routes transmitted data through the transmit path back to the clock and data recovery module of the receiving path. the loopback data are presented to the pcs in 5-bit symbol format. this loopback is used to check the operation of the 5-bit symbol decoder and the phase lock loop circuitry. in local loopback, the sd output is forced to a logica l 1 and txop/n outputs are tristated. i nterrupt m ode the intr pin on the phy is asserted whenever 1 of 8 selectable interrupt events occurs. the assertion state is high or low and is programmable through the intr_levl register bit. the selection is made by setting the appropriate bit in the upper half of the interrupt control/status register. when the intr bit goes active, the mac interface is required to read the interru pt control/status register to determine which event caused t he interrupt. the status bits are read-only and clear-on-read. when intr is not asserted, the pin is held in a high impedance state. led o peration led i nterface the led interface is fully configurable through register setting. the connection of led (source/sink current) depends on the default setting.
ac101l preliminary data sheet 8/9/04 broadcom corporation page 12 led operation document ac101l-ds06-r the default led modes are as shown below: led c onfiguration the leds are fully configurable to other operational modes. each led has two 16-bit registers to define its operation. see ?common registers? on page 22 and table 3 below to configure the leds to work with operational modes other than default mode. led [3:0] e vent t able led [3:0] are configurable. the following events are defined for ac101l operation : led0 led1 led2 led3 link/activity speed duplex collision table 3: led [3:0] event table bit# description 7duplex 6collision 5 speed 100 4 speed 10 3 transmit activity 2 transmit/receive activity 1 receive activity 0link
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r register description page 13 section 5: register description the first 7 registers of the mii register set are defined by the mii specification. in addition to these required registers the re are several registers specific to altima communications inc. there are reserved registers and/ or bits that are for altima internal use only. the following standard registers are supported ( register numbers are in decimal notation; the values are in hexadecimal notation ): legend : rw = read and write access sc = self-clearing ll = latch low until cleared by reading ro = read-only rc = cleared on read lh = latch high until cleared by reading tp phy r egister s ummary when writing to registers, it is recommended th at a read/modify/write operation be performed, as unintended bits may get set to unwanted states. this applies to all registers, including those with reserved bits. table 4: tp phy register summary register description default value registers 0?7 0 control register 3000 1 status register 7849 2 phy identifier 1 register 0022 3 phy identifier 2 register 5521 4 auto-negotiation advertisement register 01e1 5 auto-negotiation link partner ability register 0001 6 auto-negotiation expansion register 0004 7 next page advertisement register 2001 registers 8?31 8?15 reserved xxxx 16 bt and interrupt level control register 1800 17 interrupt control/status register 0000 18,19 reserved xxxx 20 cable measurement capability register xxxx 21 receive error counter register 0304 22?31 reserved xxxx
ac101l preliminary data sheet 8/9/04 broadcom corporation page 14 tp phy register summary document ac101l-ds06-r r egister 0: c ontrol r egister r egister 1: s tatus r egister table 5: register 0: control register bit name description mode default 0.15 reset 1 = phy reset. this bit is self-clearing. rw/ sc 0 0.14 loopback 1 = enable loopback mode. this loops back txd to rxd and ignores all of the activity on the cable media. 0 = normal operation. rw 0 0.13 speed select 1 = 100 mbps. 0 = 10 mbps. default value: spd100 rw set by spd100 0.12 anen enable 1 = enable the auto-negotiate process (overrides 0.13 and 0.8). 0 = disable the auto-negotiate process. mode selection is controlled via bit 0.8, 0.13. default value: anen rw set by anen 0.11 power down 1 = power down. all blocks except for smi will be turned off. setting pdown pin (24) to low will achieve the same result. 0 = normal operation. rw 0 0.10 isolate 1 = n/a. 0 = normal operation. rw 0 0.9 restart anen 1 = restart auto-negotiation process. 0 = normal operation. rw/ sc 0 0.8 duplex mode 1 = full-duplex operation. 0 = half-duplex operation. default value: !anen && duplex rw see descriptio n 0.7 collision test 1 = enable collision test that issues the col signal in response to the assertion of the txen signal. collision test is disabled if the pcsbp pin is high. collision test is enabled regardless of the duplex mode. 0 = disable col test. rw 0 0.[6:0 ] reserved ? rw 0000000 table 6: register 1: status register bit name description mode default 1.15 100base-t4 permanently tied to zero; indicates no 100base-t4 capability. ro 0 1.14 100base-tx full-duplex 1 = 100base-tx full-duplex capable. 0 = not 100base-tx full-duplex capable. default value: spd100 && duplex ro see description
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r tp phy register summary page 15 1.13 100base-tx half-duplex 1 = 100base-tx half-duplex capable. 0 = not tx half-duplex capable. default value: spd100 && (anen || !duplex). ro see description 1.12 10base-t full-duplex 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. default value: duplex && (anen || !spd100). ro see description 1.11 10base-t half-duplex 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. default value: anen || (!spd100 && !duplex). ro see description 1.[10:7] reserved ? ro 0000 1.6 mf preamble suppression the phy is able to perform management transaction without mdio preamble. the management interface needs a minimum of 32 bits of preamble after reset. ro 1 1.5 anen complete 1 = auto-negotiation process completed. registers 4, 5, and 6 are valid after this bit is set. 0 = auto-negotiation process is not completed. ro 0 1.4 remote fault 1 = remote fault condition detected. 0 = no remote fault. this bit remains set until it is cleared by reading register 1. ro/lh 0 1.3 anen ability 1 = able to perform the auto-negotiation function; default value is determined by the anen pin. 0 = unable to perform the auto-negotiation function. ro set by anen 1.2 link status 1 = link is established. if the link fails, this bit clears and remains at 0 until the register is read again. 0 = link is down. ro/ll 0 1.1 jabber detect 1 = jabber condition detected. 0 = no jabber condition detected. ro/lh 0 1.0 extended capability 1 = extended register capable. this bit is tied permanently to a value of 1. ro 1 table 6: register 1: status register (cont.) bit name description mode default
ac101l preliminary data sheet 8/9/04 broadcom corporation page 16 tp phy register summary document ac101l-ds06-r r egister 2: phy i dentifier 1 r egister r egister 3: phy i dentifier 2 r egister r egister 4: a uto -n egotiation a dvertisement r egister table 7: register 2: phy identifier 1 register bit name description mode default 2.[15:0] oui a a. based on an oui of 0010a9 (hexadecimal) composed of bits 3 ?18 of the organizationally unique identifier (oui), respectively. ro 0022(h) table 8: register 3: phy identifier 2 register bit name description mode default 3.[15:10] oui a a. based on an oui of 0010a9 (hexadecimal) assigned to bits 19 ? 24 of the oui. ro 010101 3.[9:4] model number 6-bit manufacturer?s model number. ro 010010 3.[3:0] revision number 4-bit manufacturer?s revision number. ro 0001 table 9: register 4: auto-negotiation advertisement register bit name description mode default 4.15 next page 1 = next page enabled. 0 = next page disabled. rw 0 4.14 acknowledge this bit is set internally after receiving 3 consecutive and consistent flp bursts. ro 0 4.[13:11] reserved ? 4.10 fdfc full-duplex flow control. 1 = advertise that the dte (mac) has implemented both the optional mac control sublayer and the pause function as specified in clause 31 and annex 31b of ieee 802.3u. 0 = mac does not support flow control. 4.9 100base-t4 technology not supported. this bit is always 0. ro 0 4.8 100base-tx full-duplex 1 = 100base-tx full-duplex capable. 0 = not 100base-tx full-duplex capable. default value: spd100 && duplex. rw see description 4.7 100base-tx 1 = 100base-tx half-duplex capable. 0 = not tx half-duplex capable. default value: spd100 && (anen || !duplex). rw see description 4.6 10base-t full duplex 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. default value: duplex && (anen || !spd100). rw see description
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r tp phy register summary page 17 r egister 5: a uto -n egotiation l ink p artner a bility r egister /l ink p artner n ext p age m essage r egister 6: a uto -n egotiation e xpansion r egister 4.5 10base-t 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. default value: anen || (!spd100 && !duplex). rw see descriptio n 4.[4:0] selector field protocol selection [00001] = ieee 802.3. ro 00001 table 10: register 5: auto-negotiation link part ner ability register/link partner next page message bit name description mode default 5.15 next page 1 = link partner desires a next page transfer. 0 = link partner does not desire next page transfer. ro 0 5.14 acknowledge 1 = link partner acknowledges reception of flp words. 0 = not acknowledged by the link partner. ro 0 5.[13:10] reserved ? 5.9 100base-t4 1 = 100base-t4 operation supported by the link partner. 0 = 100base-t4 operation not supported by the link partner. ro 0 5.8 100base-tx full duplex 1 = 100base-tx full-duplex operation supported by the link partner. 0 = 100base-tx full-duplex operation not supported by the link partner. ro 0 5.7 100base-tx 1 = 100base-tx half-duplex operation supported by the link partner. 0 = 100base-tx half-duplex operation not supported by the link partner. ro 0 5.6 10base-t full duplex 1 = 10 mbps full-duplex operation supported by the link partner. 0 = 10 mbps full-duplex operation not supported by the link partner. ro 0 5.5 10base-t 1 = 10 mbps half-duplex operation supported by the link partner. 0 = 10 mbps half-duplex operation not supported by the link partner. ro 0 5.[4:0] selector field protocol selection [00001] = ieee 802.3. ro 00001 note: when this register is used as the next page message, the bit definition is the same as that of register 7. table 11: register 6: auto-negotiation expansion register bit name description mode default 6.[15:5] reserved ? ro 0 table 9: register 4: auto-negotiation advertisement register (cont.) bit name description mode default
ac101l preliminary data sheet 8/9/04 broadcom corporation page 18 tp phy register summary document ac101l-ds06-r r egister 7: a uto -n egotiation n ext p age t ransmit r egister r egister 16: bt and i nterrupt l evel c ontrol r egister 6.4 parallel detection fault 1 = fault detected by parallel detection logic; this fault is due to more than one technology detecting a concurrent link-up condition. this bit can only be cleared by reading register 6, using the management interface. 0 = no fault detected by parallel detection logic. ro/lh 0 6.3 link partner next page able 1 = link partner supports next page function. 0 = link partner does not support next page function. ro 0 6.2 next page able next page is supported. ro 1 6.1 page received this bit is set when a new link code word has been received into the auto-negotiation link partner ability register. this bit is cleared upon a read of this register. rc 0 6.0 link partner anen-able 1 = link partner is auto-negotiation capable. 0 = link partner is not auto-negotiation capable. ro 0 table 12: register 7: auto-negotiation next page transmit register bit name description mode default 7.15 np 1 = another next page desired. 0 = no other next page transmit desired. rw 0 7.14 reserved ? ro 0 7.13 mp 1 = message page. 0 = unformatted page. rw 1 7.12 ack2 1 = will comply with message. 0 = cannot comply with message. rw 0 7.11 tog_tx 1 = previous value of transmitted link code word equals to 0. 0 = previous value of transmitted link code word equals to 1. rw 0 17.[10:0] code message/unformatted code field. rw 001 table 13: register 16: bt and interrupt level control register bit name description mode default 16.15 repeater 1 = repeater mode. full-duplex is inactive, and crs only responds to receive activity. sqe test function is disabled. rw set by repeater 16.14 reserved - rw 0 16.13 txjam 1 = forces cim to send jam pattern. 0 = normal operation. rw 0 16.12 reserved - ro 1 16.11 sqe test inhibit 1 = disable 10base-t sqe testing. 0 = enable 10base-t sqe testing, which generates a col pulse following the completion of a packet transmission . rw 0 16.[10:6] reserved ? ro 0 table 11: register 6: auto-negotiation expansion register (cont.) bit name description mode default
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r tp phy register summary page 19 r egister 17: i nterrupt c ontrol /s tatus r egister r egister 18: d iagnostic r egister 16.5 autopolarity disable 1 = disables autopolarity detection/correction. 0 = enables autopolarity detection/correction. rw 0 16.4 reverse polarity 1 = reverses polarity when register 16.5 = 0. 0 = normal polarity when register 16.5 = 0. if register 16.5 is set to 1, writing a 1 to this bit reverses the polarity of the transmitter. rw 0 16.[3:0] reserved ? ro 0 table 14: register 17: interrupt control/status register bit name description mode default 17.15 jabber_ie jabber interrupt enable. rw 0 17.14 rxer_ie receive error interrupt enable. rw 0 17.13 page_rx_ie page received interrupt enable. rw 0 17.12 pd_fault_ie parallel detection fault interrupt enable. rw 0 17.11 lp_ack_ie link partner acknowledge interrupt enable. rw 0 17.10 link_status_change_i e link status change interrupt enable. rw 0 17.9 r_fault_ie remote fault interrupt enable. rw 0 17.8 anen_comp_ie auto-negotiation complete interrupt enable. rw 0 17.7 jabber_int this bit is set when a jabber event is detected. rc 0 17.6 rxer_int this bit is set when rxer transitions high. rc 0 17.5 page_rx_int this bit is set when a new page is received during anen. rc 0 17.4 pd_fault_int this bit is set when parallel detect fault is detected. rc 0 17.3 lp_ack_int this bit is set when the flp with acknowledge bit set is received. rc 0 17.2 link_not_ok int this bit is set when link status switches from ok status to non-ok status (fail or ready). rc 0 17.1 r_fault_int this bit is set when remote fault is detected. rc 0 17.0 anen _comp int this bit is set when anen is complete. rc 0 table 15: register 18: diagnostic register bit name description mode default 18.[15] reserved reserved. rw 0 18.[14] reserved reserved. rw 0 18.[13] force link pass 10bt 1 = enables force link pass 10base-t. 0 = disables force link pass 10base-t. rw 0 18.[12] force link pass 100tx 1 = force link pass 100base-tx. 0 = disable force link pass 100base-tx. rw 0 18.11 reserved reserved. ro 0 table 13: register 16: bt and interrupt level control register (cont.) bit name description mode default
ac101l preliminary data sheet 8/9/04 broadcom corporation page 20 tp phy register summary document ac101l-ds06-r r egister 19: p ower /l oopback r egister r egister 20: c able m easurement c apability r egister 18.10 reserved reserved. ro 0 18.9 reserved reserved. ro 0 18.8 reserved reserved. ro/rc 0 18.[7:0] reserved reserved. ro 0 table 16: register 19: power/loopback register bit name description mode default 19.[14:7] reserved reserved. rw 00 19.6 reserved reserved. rw 0 19.5 disable watchdog timer for decipher 1 = disables watchdog timer. 0 = enables advanced power saving mode. rw 0 19.4 low power mode disable 0 = enables advanced power saving mode. 1 = disables advanced power saving mode. (do not enable this bit during normal operation). rw 0 19.3 reserved reserved. rw 0 19. 2 reserved reserved. rw 0 19.1 nlp link integrity test 1 = in auto-negotiation test mode, sends nlp instead of flp to test nlp receive integrity. 0 = sends flp in auto-negotiation test mode. rw 0 19.0 jabber disable 1 = disables jabber. rw 0 table 17: register 20: cable measurement capability register bit name description mode default 20.15 reserved reserved. rw 1 20.14 reserved 1 = on. 0 = off. rw 1 20.[13:9] reserved reserved. ro 0 a 20.8 a. to set the value of 20.[7:4], you must turn on bit 20.8 and turn off bit 20.14. otherwise, this phy rejects receive packets. adaptation disable 1 = disables adaptation. 0 = enables adaptation. rw 0 20.[7:4] cable measurement capability these bits can be used as a cable length indicator. the bits are incremented from 0000 to 1111, with an increment of approximately 10 meters. the equivalent is 0 to 32 db with an increment of 2 db @ 100 mhz. the value is a read back from the equalizer, and the measured value is not absolute. rw x 20.[3:0] reserved reserved. ro x table 15: register 18: diagnostic register (cont.) bit name description mode default
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r tp phy register summary page 21 r egister 21: r eceive e rror c ounter r egister 22: p ower m anagement r egister r egister 23: o peration m ode r egister table 18: register 21: receive error counter bit name description mode default 21.[15:0] rxer counter counts receive error events. ro 0 table 19: register 22: power management register bit name description mode default 22.[15:14] reserved ? ro 00 22.13 pd_pll 1 = pll circuit powers down. ro x 22.12 pd_equal 1 = equalizer circuit powers down. ro x 22.11 pd_bt_rcvr 1 = 10base-t receiver powers down. ro x 22.10 pd_lp 1 = link pulse receiver powers down. ro x 22.9 pd_en_det 1 = energy-detect circuit powers down. ro x 22.8 pd_fx 1 = fx circuit powers down. ro x 22.[7:6] reserved ? rw 00 22.5 msk_pll 0 = forces pll circuit to power up. 1 = pll circuit auto power-down. rw 1 22.4 msk_equal 0 = forces equalizer circuit to power up. rw x 22.3 msk_bt_rcvr 0 = forces 10base-t receiver to power up. rw x 22.2 msk_lp 0 = forces link pulse receiver to power up. rw x 22.1 msk_en_det 0 = forces energy-detect circuit to power up. rw x 22.0 msk_fx 0 = forces fx circuit to power up. rw x table 20: register 23: operation mode register bit name description mode default 23.[15:14] reserved ? 23.13 clk_rclk_save 1 = sets rclk save mode. rclk shuts off after 64 cycles of each packet. 0 23.12 reserved ? 23.11 scramble disable 1 = disables scrambler. 0 = enables scrambler. rw 0 23.10 reserved ? rw 0 23.9 pcsbp 1 = enables pcs bypass mode. 0 = disables pcs bypass mode. rw 0 23:8 reserved ? rw 0 23.7 auto-mdix disable 0 = auto-mdix mode. 1 = disable auto-mdix mode. rw 0
ac101l preliminary data sheet 8/9/04 broadcom corporation page 22 common registers document ac101l-ds06-r r egister 24: crc for r ecent r eceived p acket c ommon r egisters the following registers are mapped to reg28-31 on the tp phy. reg28.[15:12] is used as page selection. there are multiple pages of reg29-31, depends on the value of reg28[15:12]. c ommon r egister 0 (m ap to r eg 28) m ode c ontrol r egister 23.6 mdix state only valid when register 23.7 is set to 1. 0 = mdi 1= mdix rw 0 23.5 reserved ? ro 0 23.[4:0] reserved ? ro xxxxx table 21: register 24: crc for recent received packet bit name description mode default 24.[15:0] crc16 displays crc16 value. for system-level test purposes. rc 0000h table 22: common register 0 (map to reg. 28) mode control register bit name description mode default a.28.[15:12 ] page selection selects multiple common register pages. rw 0000 a.28.[11:7] reserved reserved. ro 0000 a.28.6 mii_enable 1 = enables mii interface. rw 1 a.28.5 reserved reserved. ro 0 a.28.4 reserved reserved. rw 0 a.28.3 reserved reserved. ro 0 a.28.2 act select selects activity event. 0 = receive activity. 1 = tx or rx activity. rw 1 a.28.1 reserved ? ro 0 a.28.0 reserved ? ro 0 table 20: register 23: operation mode register (cont.) bit name description mode default
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r common registers page 23 c ommon r egister 1: (m ap to r eg . 29, p age 0 a28.[15:12]=0000) t est m ode r egister c ommon r egister 4: (m ap to r eg . 29, p age 1 a28.[15:12]=0001) led b link r ate c ommon r egister 5: (m ap to r eg . 30, p age 1 a.28.[15:12]=0001) led0 s etting 1 r egister default operation for led0 is on when link; blink when activity. table 23: common register 1: (map to reg. 29, page 0 a28.[15:12]=0000) test mode register bit name description mode default a0.29.15 reduce_mcou nt reduces millisecond counter to 256 microseconds. ro 0 a0.29.[14:10 ] reserved ? ro 00100 a0.29.[9:8] reserved ? rw 00 a0.29.[7:4] test mode 0000 = normal operation. rw 0000 a0.29.3 burn in 1 = enables burn-in test mode. 0 = normal operation. rw 0 a0.29.2 output disable 1 = disables all digital output. 0 = normal operation. rw 0 a0.29.1 reserved 0 = normal operation. rw 0 a0.29.0 reduce timer 1 = reduces timer for auto-negotiation testing. 0 = normal operation. rw 0 table 24: common register 4: (map to reg. 29, page 1 a28.[15:12]=0001) led blink rate bit name description mode default a1.29.[15:8] reserved ? ro 00000000 a1.29.[7:0] blink rate set led blink rate. the blink rate is this number 16 ms. default value is 256 ms. rw 00010000 table 25: common register 5: (map to reg. 30, page 1 a.28.[15:12]=0001) led0 setting1 register bit name description mode default a1.30.[15:13] reserved ? rw 0000 a1.30.12 force led on forces led0 on. rw 0 a1.30.[11:9] reserved ? rw 000 a1.30.8 force led off forces led0 off. rw 0 a1.30.[7:0] msk blink blink mask. when the bits are set to 1, a corresponding event causes the led to blink. rw 00000100
ac101l preliminary data sheet 8/9/04 broadcom corporation page 24 common registers document ac101l-ds06-r c ommon r egister 6: (m ap to r eg . 31, p age 1 a.28.[15:12]=0001) led0 s etting 2 r egister c ommon r egister 7: (m ap to r eg . 29, p age 2 a.28.[15:12]=0010) led1 s etting 1 r egister c ommon r egister 8: (m ap to r eg . 30, p age 2 a.28.[15:12]=0010) led1 s etting 2 r egister default operation for led1 is on during 100 mbps operation. c ommon r egister 9: (m ap to r eg . 31, p age 2 a.28.[15:12]=0010) led2 s etting 1 r egister table 26: common register 6: (map to reg. 31, page 1 a.28.[15:12]=0001) led0 setting2 register bit name description mode default a1.31. [15:8] msk on on mask. when the bits are set to 1, a corresponding event causes the led to turn on. rw 00000001 a1.31. [7:0] msk off off mask. when the bits are set to 1, a corresponding event causes the led to turn off. rw 00000000 table 27: common register 7: (map to reg. 29, page 2 a.28.[15:12]=0010) led1 setting1 register bit name description mode default a2.29.[15:13] reserved ? ro 000 a2.29.12 force led on forces led1 on. rw 0 a2.29.[11:9] reserved ? ro 000 a2.29.8 force led off forces led1 off. rw 0 a2.29.[7:0] msk blink blink mask. when the bits are set to 1, a corresponding event causes the led to blink. rw 00000000 table 28: common register 8: (map to reg. 30, page 2 a.28.[15:12]=0010) led1 setting2 register bit name description mode default a2.30.[15:8] msk on on mask. when the bits are set to 1, a corresponding event causes the led to turn on. rw 00100000 a2.30.[7:0] msk off off mask. when the bits are set to one, a corresponding event causes the led to turn off. rw 00000000 table 29: common register 9: (map to reg. 31, page 2 a.28.[15:12]=0010) led2 setting1 register bit name description mode default a2.31.[15:13] reserved ? ro 000 a2.31.12 force led on forces led2 on. rw 0 a2.31.[11:9] reserved ? ro 000 a2.31.8 force led off forces led2 off. rw 0
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r common registers page 25 c ommon r egister 10: (m ap to r eg . 29, p age 3 a.28.[15:12]=0011) led2 s etting 2 r egister default operation for led2 is on during duplex mode operation. . c ommon r egister 11: (m ap to r eg . 30, p age 3 a.28[.15:12]=0011) led3 s etting 1 r egister default operation for led3 is blink when col. c ommon r egister 12: (m ap to r eg . 31, p age 3 a.28.[15:12]=0011) led3 s etting 2 r egister a2.31.[7:0] msk blink blink mask. when the bits are set to 1, a corresponding event causes the led to blink. rw 00000000 table 30: common register 10: (map to reg. 29, page 3 a.28.[15:12]=0011) led2 setting2 register bit name description mode default a3.29.[15:8] msk on on mask. when the bits are set to 1, a corresponding event causes the led to turn on. rw 10000000 a3.29.[7:0] msk off off mask. when the bits are set to 1, a corresponding event causes the led to turn off. rw 00000000 table 31: common register 11: (map to reg. 30, page 3 a.28[.15:12]=0011) led3 setting1 register reg.bit name description mode default a3.30.[15:13] reserved ? ro 000 a3.30.12 force led on forces led3 on. rw 0 a3.30.[11:9] reserved ? ro 000 a3.30.8 force led off forces led3 off. rw 0 a3.30.[7:0] msk blink blink mask. when the bits are set to 1, a corresponding event causes the led to blink. rw 0100000 table 32: common register 12: (map to reg. 31, page 3 a.28.[15:12]=0011) led3 setting2 register bit name description mode default a3.31.[15:8] msk on on mask. when the bits are set to 1, a corresponding event causes the led to turn on. rw 00000000 a3.31.[7:0] msk off off mask. when the bits are set to 1, a corresponding event causes the led to turn off. rw 00000000 table 29: common register 9: (map to reg. 31, page 2 a.28.[15:12]=0010) led2 setting1 register (cont.) bit name description mode default
ac101l preliminary data sheet 8/9/04 broadcom corporation page 26 4b/5b code group document ac101l-ds06-r section 6: 4b/5b code group table 33: 4b/5b code group symbol name 4b code 5b code description 0 0000 11110 data 0 1 0001 01001 data 1 2 0010 10100 data 2 3 0011 10101 data 3 4 0100 01010 data 4 5 0101 01011 data 5 6 0110 01110 data 6 7 0111 01111 data 7 8 1000 10010 data 8 9 1001 10011 data 9 a 1010 10110 data a b 1011 10111 data b c 1100 11010 data c d 1101 11011 data d e 1110 11100 data e f 1111 11101 data f idle and control codes i 0000 11111 idle j 0101 11000 start-of-stream delimiter, part 1 of 2; always use in pair with k symbol k 0101 10001 start-of-stream delimiter, part 2 of 2; always use in pair with j symbol t undefined 01101 end-of-stream delimiter, part 1 of 2; always use in pair with r symbol r undefined 00111 end-of-stream delimiter, part 2 of 2; always use in pair with t symbol invalid code h undefined 00100 transmit error; used to send halt code group v undefined 00000 invalid code v undefined 00001 invalid code v undefined 00010 invalid code v undefined 00011 invalid code v undefined 00101 invalid code v undefined 00110 invalid code v undefined 01000 invalid code v undefined 01100 invalid code v undefined 10000 invalid code v undefined 11001 invalid code
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r smi read/write sequence page 27 section 7: smi read/write sequence table 34: smi read/write sequence smi read/write sequence ?pream (32 bits) start (2 bits) opcode (2 bits) phyad (5 bits) regad (5 bits) turnaround (2 bits) data (16 bits) idle read 1?1 01 10 aaaaa rrrrr z0 d?d z write 1?1 01 01 aaaaa rrrrr 10 d?d z
ac101l preliminary data sheet 8/9/04 broadcom corporation page 28 timing and ac characteristics document ac101l-ds06-r section 8: timing and ac characteristics c lock t iming r eset t iming figure 3: reset timing table 35: clock timing parameter symbol min typ max units xtal input cycle time ck_cycle ? 40 ? ns xtal input high/low time ck_hi ck_lo ? 20 ? ns xtal input rise/fall time ck_edge ? ? 4 ns table 36: reset timing parameter symbol min typ max units reset pulse length low period with stable xtal input reset_len 1 ? ? s activity after end of hardware reset reset_wait 1 ? ? seconds reset rise/fall time reset_edge ? 5 10 ns xtal input reset# normal phy reset_len reset_wait ck_hi ck_cycle ck_edge ck_lo ck_edge activity begins here reset_edge reset_edge
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r management data interface timing page 29 m anagement d ata i nterface timing figure 4: management interface timing 100base-tx/fx mii t ransmit s ystem t iming table 37: management interface timing parameter symbol min typ max units mdc cycle time mdc_cycle 40 ? ? ns mdc high/low ? 20 ? ? ns mdc rise/fall time mdc_rise mdc_fall ? ? 10 ns mdio input setup time to mdc rising mdio_setup 10 ? ? ns mdio input hold time from mdc rising mdio_hold 10 ? ? ns mdio output delay from mdc rising mdio_delay 0 ? 30 ns table 38: 100base-x mii transmit system timing parameter symbol conditions min typ max units tx_clk period tck ? 39.998 40.000 40.002 ns tx_clk high period tckh ? 18.000 20.000 22.000 ns tx_clk low period tckl ? 18.000 20.000 22.000 ns txen to /j/ ttj ? ? 60 140 ns txen sampled to crs tcsa rptr is logic low ? 60 140 ns txen sampled to col tcla rptr is logic low ? 60 140 ns !txen to /t/ ttt ? ? 60 140 ns !txen sampled to !crs tcsd rptr is logic low ? 60 140 ns !txen sampled to !col tcld rptr is logic low ? 60 140 ns tx propagation delay ttj from txd[3:0] to txop/n(fxtp/n) ? 60 140 ns mdio (from ac101l) mdc mdc_fall mdio_hold mdio_setup mdc_rise mdc_cycle mdio_setup mdio_hold mdio_delay mdio (into ac101l )
ac101l preliminary data sheet 8/9/04 broadcom corporation page 30 100base-tx/fx mii transmit system timing document ac101l-ds06-r figure 5: 100base-tx/fx mii transmit timing txd[3:0], txen, txer setup ttxs from rising edge of tx_clk 10 ? ? ns txd[3:0], txen, txer hold ttxh from rising edge of tx_clk 0 ? 25 ns table 38: 100base-x mii transmit system timing (cont.) parameter symbol conditions min typ max units f xtp/n t x_clk t xen t xd[3:0] t x_er t xop/n /j/ /t/ tck tckh tckl ttxs ttxh ttj ttt c rs c ol ttcsa ttcsd ttcla ttcld start of packet end of packet
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r 100base-tx/fx mii transmit system timing page 31 100base-tx/fx mii r eceive s ystem t iming table 39: 100base-tx/fx mii receive system timing parameter symbol conditions min typ max units rx_clk period tck ? 39.998 40.000 40.002 ns rx_clk high period tckh ? 18.000 20.000 22.000 ns rx_clk low period tckl ? 18.000 20.000 22.000 ns /j/k to rxdv assert trdva ? ? 40 180 ns /j/k to crs assert trcsa ? ? 40 180 ns /j/k to col assert trcla rptr is logic low. ? 40 180 ns /t/r to !rxdv trdvd rptr is logic low. ? 40 180 ns /t/r to !crs trcsd rptr is logic low. ? 40 180 ns /t/r to !col trcld rptr is logic low. ? 40 180 ns rx propagation delay trdva from rxip/n(fxrp/n) to rxd[3:0]. ? 40 180 ns rxd[3:0], rxdv assert: output delay tplh 100 from rising edge rx_clk. 10 ? 30 ns rxd[3:0], rxdv de-assert: invalid tphl 100 from rising edge rx_clk. 10 ? 30 ns
ac101l preliminary data sheet 8/9/04 broadcom corporation page 32 100base-tx/fx mii transmit system timing document ac101l-ds06-r figure 6: 100base-t mii receive timing fxrp/n rx_clk rxdv rxd[3:0] rxer rxdv rxip/n /j/k /t/r tck tckh tckl trdva - crs col trcsa trcsd trcla trcld start of packet end of packet trdvd tplh = output delay tplh100 rx_clk rxd[3:0]; rxdv 25mhz tphl100 tphl = invalid valid data tck tckh tckl
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r 10base-t mii transmit system timing page 33 10base-t mii t ransmit s ystem t iming figure 7: 10base-t transmit timing table 40: 10base-t mii transmit system timing parameter sym conditions min typ max units tx_clk period tck ? 399.98 400.00 400.02 ns tx_clk high period tckh ? 180.00 200.00 220.00 ns tx_clk low period tckl ? 180.00 200.00 220.00 ns txen to sop ttj ? 240 ? 360 ns txen sampled to crs ttcsa rptr is logic low ? ? 130 ns txen sampled to col ttcla rptr is logic low ? ? 300 ns !txen to eop ttj ? 240 ? 360 ns !txen sampled to !crs ttcsd rptr is logic low ? ? 130 ns !txen sampled to !col ttcld rptr is logic low ? ? 300 ns tx propagation delay ttj from txd[3:0] to txop/n 240 ? 360 ns txd[3:0], txen, txer setup ttxs from rising edge of tx_clk 10 ? ? ns txd[3:0], txen, txer hold ttxh from rising edge of tx_clk 0 ? ? ns ttx_t x c rs t x_clk t xen t xd[3:0] t x_er t xop/n c ol tck tckh tckl ttxs ttxh ttcs a ttcs d ttcla ttcld start of packet end of packet tt j tt j ttj ttj ttx_tx ttcsd ttcsa
ac101l preliminary data sheet 8/9/04 broadcom corporation page 34 10base-t mii receive system timing document ac101l-ds06-r 10base-t mii r eceive s ystem t iming table 41: 10base-t mii receive system timing parameter symbol conditions min typ max units rx_clk period tck ? 399.98 400.00 400.02 ns rx_clk high period tckh ? 180.00 200.00 220.00 ns rx_clk low period tckl ? 180.00 200.00 220.00 ns sop to crs trcsa ? 80 ? 150 ns sop to col trcla rptr is logic low. 80 ? 150 ns eop to !rxdv trdvd rptr is logic low. 120 ? 140 ns eop to !crs trcsd rptr is logic low. 130 ? 190 ns eop to !col trcld rptr is logic low. 125 ? 185 ns rx propagation delay trdva from rxip/n to rxd[3:0]. 180 ? 250 ns rxd[3:0], rxdv assert: output delay tplh 10 from rising edge rx_clk. 50 ? 350 ns rxd[3:0], rxdv de-assert: invalid tphl 10 from rising edge rx_clk. 50 ? 350 ns
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r 10base-t mii receive system timing page 35 figure 8: 10base-t receive timing tplh=output delay tplh10 rx_clk rxd[3:0]; rxdv 25mhz tphl10 tphl=invalid valid data tck tckh tckl c rs r x_clk r xdv r xd[3:0] r xer r xdv c ol tck tckh tckl trcsd trdva trcsa trcla trcld start of packet end of packet trdvd r xip/n sop eop
ac101l preliminary data sheet 8/9/04 broadcom corporation page 36 copper application termination document ac101l-ds06-r c opper a pplication t ermination figure 9: tx application 4 txp 2 txn auto mdi/mdix rj45 3 ac101l 1 8 6 7 rxn 5 auto mdi/mdix magnetics: bel: s558-5999-w2; pulse: h1102; halo: tg110-s050n2 rxp 1:1 1:1 2.5 v 2.5 v c2 0.1 f c4 0.1 f c3 0.1 f r7 75 ? _1/16w_5% r5 75 ? _1/16w_5% c1 0.1 f r4 49.9 ? _1/16w_1% r8 75 ? _1/16w_5% c5 1000pf_2kv r1 49.9 ? _1/16w_1% r2 49.9 ? _1/16w_1% r6 75 ? _1/16w_5% r3 49.9 ? _1/16w_1%
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r electrical characteristics page 37 section 9: electrical characteristics a bsolute m aximum r atings note: the following electrical characteristics are design goals rather than characterized numbers. table 42: absolute maximum ratings parameter symbol min max units supply voltage 3v3 gnd-0.3 3.465 v storage temperature ts ?40 +125 c electrostatic discharge vesd ? 1000 v table 43: current requirement at 2.5v operation with led disabled operational mode current (ma) @v cc = 2.5v @v cc = 2.625v traffic at 100 mbps 90 100 power-down ? 16 standby 30 32 table 44: current requirement at 3.3v operation with led disabled operational mode current (ma) @v cc = 3.3v @v cc = 3.465v traffic at 100 mbps 92 102 power-down ? 18 standby 32 34
ac101l preliminary data sheet 8/9/04 broadcom corporation page 38 recommended operating conditions document ac101l-ds06-r r ecommended o perating c onditions table 45: recommended operating conditions parameter symbol pins operating mode min typ max units ambient operating temperature ac101l t a ? ? ?40 ? +85 c bias voltage v bias rbiad ? 1.18 ? 1.30 v common mode input voltage v icm rd 100base-tx 1.8 ? vcc v common mode input voltage v icm rd 100base-fx 1.8 ? 2.2 v differential input voltage v idiff rd 100base-fx (with 100 ohm load) 0.37 ? 2.00 v differential output voltage v odiff td 100base-fx mode 1.5 ? 1.7 v input current i i digital inputs with pull-up resistor v i = vcc ? ? 200 a input voltage high v ih sd 100base-fx 2.2 ? ? v input voltage high v ih all digital input v cc = 2.5v 5% 1.4 ? ? v input voltage low v il sd 100base-fx ? ? 1.7 v input voltage low v il all digital input v cc = 2.5v 5% ? ? 1.1 v output voltage high v oh all digital output v cc = 2.5v 5% i oh = ?10 a 2.3 ? ? v output voltage high v oh all digital output v cc = 2.5v 5% i oh = ?4 ma 2.0 ? ? ? output voltage high v oh td driving load magnetic module ? ? vcc+1.5 v output voltage low v ol all digital output v cc = 2.5 v 5% i ol = 10 a ??0.4? output voltage low v ol all digital output v cc = 2.5v 5% i ol = 4 ma ??0.4? output voltage low v ol td driving load magnetic module v cc ?1.5 ? ? ? supply voltage ac101l 3v3 vcc33in ? 3.135 3.3 3.465 v supply voltage ac101l v cc vcc, vccpll, vcc25out ? 2.375 2.5 2.625 v
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r fiber application termination page 39 section 10: fiber application termination figure 10: fx application z=50 ohm z=50 ohm z=50 ? z=50 ? z=50 ? z=50 ? z=50 ? z=50 ? txn txp sd/fxen rxn rxp 3_3 v 2_5 v 3_3 v 3_3 v c9 0.1 f c4 0.01 f l2 blm11a601s l1 blm11a601s u1 hfbr-5903 9 3 4 5 10 2 6 1 7 8 td+ sd rd- rd+ td- rxvcc txvcc rxvee txvee nc r15 82 r5 50 ? c8 0.1 f r11 20 k ? r9 130 ? c1 0.1 f c6 0.1 f c7 0.1 f r1 130 ? r12 20 k ? r14 20 k ? r7 13 k ? r3 5k ? r6 13 k ? r16 82 c5 0.01 f c3 10 f c2 0.1 f c12 1 f c11 0.1 f r2 5k ? r4 50 ? c10 0.1 f r13 20 k ? r8 130 ? r10 82 ? ac101l z=50 ?
ac101l preliminary data sheet 8/9/04 broadcom corporation page 40 power and ground filtering document ac101l-ds06-r section 11: power and ground filtering figure 11: power and ground filtering place all caps as close as possible to each power pin of ac101l vccpll 2_5 v 2_5 v 2_5 v 2_5 v 2_5 v 3_3 v c10 1 nf c4 0.1 f c1 10 f c3 0.01 f c15 0.1 f c9 0.1 f + c11 2.2 f c8 0.01 f 4 8 tqfp_7x7mm ac101l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vcc gnd1 rxdv/crsdv rxc rxer gnd2 vcc txer txc txen txd0 txd1 txd2 txd3 col crs/repeater gnd3 vcc intr/phyad0 led0/burnin_l led1/spd100 led2/duplex led3/anen pdown vcc rxn rxp sd/fxen gnd4 gnd5 rbiad vccpll gnd6 txn txp vcc25out gnd7 gnd8 xo xi vcc33in rst_l mdio mdc rxd3/phyad1 rxd2/phyad2 rxd1/phyad3 rxd0/phyad4 c1 3 0.1 f c14 0.01 f c5 22 f c12 0.01 f c2 0.1 f c7 0.1 f c6 1 f c16 0.01 f
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r mechanical information page 41 section 12: mechan ical information figure 12: quad flat pack outline (77 mm)
ac101l preliminary data sheet 8/9/04 broadcom corporation page 42 thermal parameters document ac101l-ds06-r section 13: thermal parameters table 46: thermal parameters airflow (feet per minute) 0 100 200 400 600 theta ja ( c/w) 53.9 51.2 50 48.6 47.5 theta jc ( c/w) at maximum junction temperature of 125 c24.7? ?
preliminary data sheet ac101l 8/9/04 broadcom corporation document ac101l-ds06-r ordering information page 43 section 14: ordering information table 47: ordering information part number package ambient temperature ac101lkqt 48tqfp 0 c to +70 c ac101liqt 48tqfp ?40 c to +85 c
ac101l preliminary data sheet 8/9/04 document ac101l-ds06-r altima communications, inc. a wholly-owned subsidiary of broadcom corporation 16215 alton parkway p.o. box 57013 irvine, california 92619-7013 phone: 949-450-8700 fax: 949-450-8710 altima communications reserves the right to make changes without further notice to any products or data herein to improve relia bility, function, or design. information furnished by altima communications is believed to be accurate and reliable. however, altima communications does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

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